View ICS85322_331910.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
FEATURES
* 2 differential 2.5V/3.3V LVPECL outputs * Selectable CLK0, CLK1 LVCMOS clock inputs * CLK0 and CLK1 can accepts the following input levels: LVCMOS or LVTTL * Maximum output frequency up to 267MHz * Part-to-part skew: 150ps (maximum) * 3.3V operating supply voltage (operating range 3.135V to 3.465V) * 2.5V operating supply voltage (operating range 2.375V to 2.625V) * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
ICS85322
GENERAL DESCRIPTION
The ICS85322 is a Dual LVCMOS / LVTTL-toDifferential 2.5V / 3.3V LVPECL translator and a HiPerClockSTM member of the HiPerClocksTM family of High Performance Clocks Solutions from ICS. The ICS85322 has selectable single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 2.5V / 3.3V LVPECL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.
,&6
BLOCK DIAGRAM
CLK0 Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VCC CLK0 CLK1 VEE
CLK1
ICS85322
8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View
85322AM
www.icst.com/products/hiperclocks.html
1
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Type Output Output Power Input Input Power Pullup Pullup Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Connect to ground. LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input. Positive supply pin. Connect to 3.3V or 2.5V
ICS85322
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 VEE CLK1 CLK0 VCC
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor CLK0, CLK1 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
85322AM
www.icst.com/products/hiperclocks.html
2
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
4.6V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 112.7C/W (0lfpm)
ICS85322
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 25 Units V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 VCC = VIN = 3.465V VCC = VIN = 3.465V -150 Test Conditions Minimum 2 -0.3 Typical Maximum 3.765 1.3 5 Units V V A A
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V Minimum VCC - 1.4 VCC - 2.0 0.65 Typical Maximum VCC - 1.0 VCC - 1.7 0.9 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
85322AM
www.icst.com/products/hiperclocks.html
3
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Test Conditions 267MHz 20% to 80% @ 50MHz 20% to 80% @ 50MHz Minimum 0.6 300 300 Typical Maximum 267 1.8 150 700 700 60 Units MHz ns ps ps ps %
ICS85322
TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise Time Output Fall Time
t sk(pp)
tR tF
odc Output Duty Cycle 40 All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from the 50% point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85322AM
www.icst.com/products/hiperclocks.html
4
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 25 Units V mA
ICS85322
TABLE 3D. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V5%, TA = 0C TO 70C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current
TABLE 3E. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 VCC = VIN = 2.625 VCC = VIN = 2.625 -150 Test Conditions Minimum 1.6 -0.3 Typical Maximum 2.925 0.9 5 Units V V A A
TABLE 3F. LVPECL DC CHARACTERISTICS, VCC = 2.5V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.65 Typical Maximum VCC - 1.0 VCC - 1.7 0.9 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4B. AC CHARACTERISTICS, VCC = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 215MHz 0.8 Test Conditions Minimum Typical Maximum 215 2 150 700 700 60 Units MHz ns ps ps ps %
tsk(pp)
tR tF
odc Output Duty Cycle 40 All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from the 50% point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65..
85322AM
www.icst.com/products/hiperclocks.html
5
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
ICS85322
PARAMETER MEASUREMENT INFORMATION
V CC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE = -1.3V 0.135V
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
V CC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE = -0.5V 0.125V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
85322AM
www.icst.com/products/hiperclocks.html
6
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
ICS85322
Qx PART 1 nQx
Qy PART 2 nQy
tsk(pp)
FIGURE 2 - PART-TO-PART SKEW
80%
80% V
SWING
20% Clock Inputs and Outputs t t
AND
20%
R
F
FIGURE 3 - INPUT
OUTPUT RISE
AND
FALL TIME
85322AM
www.icst.com/products/hiperclocks.html
7
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
V /2
CC
ICS85322
CLK0, CLK1
Q0 - Q1 nQ0 - nQ1
t
PD
FIGURE 4 - PROPAGATION DELAY
CLK0, CLK1, Q0, Q1 nQ0, nQ1
Pulse Width t t odc = t
PW PERIOD
PERIOD
FIGURE 5 - odc & tPERIOD
85322AM
www.icst.com/products/hiperclocks.html
8
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR POWER CONSIDERATIONS
ICS85322
This section provides information on power dissipation and junction temperature for the ICS85322. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85322 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.147W * 103.3C/W = 85.2C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 5. Thermal Resistance qJA for 8-pin SOIC, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0 Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7C/W 200 128.5C/W 103.3C/W 500 115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85322AM
www.icst.com/products/hiperclocks.html
9
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
ICS85322
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 6 - LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L L
CC_MAX
-V
OH_MAX
)
Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) * For logic high, VOUT = V Using V *
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
OH_MAX
= 3.465, this results in V =V
= 2.465V
For logic low, VOUT = V Using V
CC_MAX
OL_MAX
CC_MAX
- 1.7V
OL_MAX
= 3.465, this results in V
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50] * (3.465V - 2.465V) = 20mW Pd_L = [(1.765V - (3.465V - 2V))/50] * (3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85322AM
www.icst.com/products/hiperclocks.html
10
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR RELIABILITY INFORMATION
ICS85322
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0 Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7C/W 200 128.5C/W 103.3C/W 500 115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85322 is: 269
85322AM
www.icst.com/products/hiperclocks.html
11
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
ICS85322
PACKAGE OUTLINE - M SUFFIX
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
85322AM
www.icst.com/products/hiperclocks.html
12
REV. A JULY 31, 2001
Integrated Circuit Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Marking ICS85322AM ICS853322AM Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature 0C to 70C 0C to 70C
ICS85322
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85322AM ICS85322AM-T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85322AM
www.icst.com/products/hiperclocks.html
13
REV. A JULY 31, 2001

▲Up To Search▲

Price & Availability of ICS85322

	To Download ICS85322 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .